The present invention relates generally to the field of integrated circuits, and more particularly, to an interposer assembly apparatus and method.
Semiconductor die have traditionally been electrically connected to a package by wire bonding techniques, in which wires are attached to pads of the die and to pads located in the cavity of the plastic or ceramic package. Wire bonding is still the interconnection strategy most often used in the semiconductor industry today. But the growing demand for products that are smaller, faster, less expensive, more reliable and have a reduced thermal profile has pushed wire bonding technology to its limits (and beyond) thereby creating barriers to sustained product improvement and growth.
The high-performance alternative to wire bonding techniques are flip chip techniques, in which solder balls or bumps are attached to the input/output (I/O) pads of the die at the wafer level. The bumped die is flipped over and attached to a substrate xe2x80x9cface down,xe2x80x9d rather than xe2x80x9cface upxe2x80x9d as with wire bonding. Flip chips resolve many, if not all, of the problems introduced by wire bonding. First, flip chips have fewer electrical interconnects than wire bonding, which results in improved reliability and fewer manufacturing steps, thereby reducing production costs. Second, the face down mounting of a flip chip die on a substrate allows superior thermal management techniques to be deployed than those available in wire bonding. Third, flip chips allow I/O to be located essentially anywhere on the die, within the limits of substrate pitch technology and manufacturing equipment, instead of forcing I/O to the peripheral of the die as in wire bonding. This results in increased I/O density and system miniaturization.
Despite the advantages of the flip chip, wide spread commercial acceptance of the flip chip has been hindered by testing issues. To ensure proper performance, the die should be adequately tested before it is assembled into a product; otherwise, manufacturing yields at the module and system level can suffer and be unacceptably low. Under some circumstances, a defective die can force an entire subassembly to be scrapped. One attempt to address this testing issue has been to perform a wafer probe, followed by dicing the wafer and temporarily packaging each die into a test fixture of some sort. Performance testing is subsequently executed. Burn-in testing is often included in this process to eliminate any die having manufacturing process defects. Following the successful completion of these tests, the die are removed from the test fixture and either retailed as a Known Good Die (xe2x80x9cKGDxe2x80x9d) product or used by the manufacturer in an end product, such as a Flip Chip Module (xe2x80x9cFCMxe2x80x9d). The Flip Chip Module may constitute a subassembly in a larger system product. This Known Good Die process is inherently inefficient due to its complexity.
Accordingly, there is a need for an interposer assembly apparatus and method that meets all of the criteria outlined above, and that allows testing at the wafer level before dicing, and eliminates the need for temporarily packaging the die in a carrier.
Two characteristics that are important when selecting a material to form an interposer substrate are the coefficient of thermal expansion (CTE), and the ability to be planed to a high degree of flatness. The CTE of the material chosen should be close to that of a silicon wafer if the end use will be subjected to a range of temperatures, and the planarity should be as flat as possible, in any event, at least as flat as the semiconductor wafer the interposer substrate will be attached to. The material used for the interposer substrate should also be structurally sound and capable of being patterned with traces, connectivity pads and vias. It should also be capable of withstanding the temperatures required to solder the finished semiconductor circuit to a printed circuit board.
The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. Eliminating the need to singulate and package the dies before testing results in a significant cost avoidance opportunity for chip manufacturers. The fact that the use of the wafer-interposer accomplishes all of this while providing cost effective packaging is another substantial benefit of the present invention.
The ceramic substrate of the present invention has a good coefficient of thermal expansion that is close to that of a silicon wafer. Moreover, the ceramic substrate can be planed to a high degree of flatness and is capable of being patterned with traces, connectivity pads and electrical passageways or vias. The ceramic substrate also is capable of withstanding the temperatures required to solder the finished semiconductor circuit to a printed circuit board.
The interposer assembly of the present invention revolutionizes the semiconductor fabrication process by enabling burn-in and electrical testing at the wafer level. The interposer eliminates the need to singulate, package, test, and unpackage each die in order to arrive at the Known Good Die product stage. The interposer remains attached to the die following dicing, and thus provides the additional benefit of redistributing the die I/O pads so that they can be larger and more easily accessed and/or mated to other downstream components.
One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.
Another form of the present invention provides an interposer assembly that includes a ceramic substrate having an upper and a lower surface with one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. One or more electrical pathways connect the first and second electrical contacts. A semiconductor wafer, including one or more semiconductor dies, and having an upper surface and lower surface with one or more third electrical contacts on the first surface. There are one or more third electrical contacts on the upper surface of the semiconductor wafer, the third electrical contacts being associated with the semiconductor dies. A conductor electrically connects each first electrical contact with a corresponding third electrical contact, and a layer of no-flow underfill is disposed between the upper surface of the semiconductor wafer and the lower surface of the ceramic substrate.
Yet another form of the present invention is a method for producing an interposer substrate that includes the steps of creating one or more electrical pathways passing through a ceramic substrate having an upper surface and a lower surface. One or more first electrical contacts are attached to the one or more electrical pathways on the lower surface of the ceramic substrate. One or more second electrical contacts are attached to the one or more electrical pathways on the upper surface of the ceramic substrate.
Still another form of the present invention provides a method for producing an interposer assembly. It includes the steps of creating one or more electrical pathways passing through a ceramic substrate having an upper surface and a lower surface. One or more first electrical contacts are attached to the one or more electrical pathways on the lower surface of the ceramic substrate. One or more second electrical contacts are attached to the one or more electrical pathways on the upper surface of the ceramic substrate. A conductor and a no-flow underfill are deposited and the ceramic substrate is bonded to a semiconductor wafer such that the conductor and the no-flow underfill form an adhesive bond between the lower side of the ceramic substrate and the upper side of the semiconductor wafer.